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Low Pin Count Demo Board User’s Guide
3.2.4.1
ADCON1
ADCON1 selects the ratio between processor clock speed and conversion speed. This
is important because the ADC needs at least 1.6 μ s per bit. Accuracy degrades if the
clock speed is too high. As the processor clock speed increases, an increasingly large
divider is necessary to keep the conversion speed. Four MHz is fastest at 8:1 ratio with
a conversion speed of 2 μ s per bit. Refer to the “T AD vs. Device Operating
Frequencies” Table in the Analog-to-Digital Section of the PIC16F685/687/689/690
Data Sheet (DS41262) for recommended configurations.
REGISTER 3-1:
ADCON1 – A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)
U-0
—
R/W-0
ADCS2
R/W-0
ADCS1
R/W-0
ADCS0
U-0
—
U-0
—
U-0
—
U-0
—
bit 7
bit 0
bit 7
bit 6-4
bit 3-0
Unimplemented: Read as ‘ 0 ’
ADCS<2:0>: A/D Conversion Clock Select bits
000 = F OSC /2
001 = F OSC /8
010 = F OSC /32
x11 = F RC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = F OSC /4
101 = F OSC /16
110 = F OSC /64
Unimplemented: Read as ‘ 0 ’
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
- n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
DS51556A-page 20
? 2005 Microchip Technology Inc.
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